Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a circuit which generates an internal clock signal by buffering an external clock signal.
In general, in a synchronous semiconductor device, such as a synchronous DRAM (SDRAM), an internal clock signal is generated by buffering an external clock signal, and a predetermined operation is performed using the generated internal clock signal.
At this time, in a procedure of generating the internal clock signal by buffering the external clock signal, the buffering operation should be able to be on/off controlled depending upon a clock enable signal. This is because most semiconductor devices support an operation mode for generating an internal clock signal in correspondence to an external clock signal, for example, a power down mode, in order to reduce current consumption.
FIG. 1 is a circuit diagram illustrating in detail a conventional circuit for generating an internal clock signal by buffering an external clock signal.
Referring to FIG. 1, a conventional circuit for generating an internal clock signal by buffering an external clock signal includes a synchronization section 100 which is configured to synchronize a clock enable signal CKE in response to an external clock signal EXT_CLK, and an internal clock generation section 120 which is configured to generate an internal clock signal INT_CLK corresponding to the external clock signal EXT_CLK and is on/off controlled in its operation in response to a synchronized clock enable signal SYNC_CKE that is outputted from the synchronization section 100.
The synchronization section 100 includes a pass gate PG and an inverter INV1. The pass gate PG is configured to receive the external clock signal EXT_CLK through a negative input terminal and a clock signal/EXT_CLK obtained by inverting the phase of the external clock signal EXT_CLK through a positive input terminal. Further, the pass gate PG is configured to control the transmission of the clock enable signal CKE applied through a signal input terminal to a signal output terminal as the synchronized clock enable signal SYNC_CKE.
The internal clock generation section 120 includes a NAND gate NAND and an inverter INV2. The NAND gate NAND is configured to receive the external clock signal EXT_CLK through a first input terminal and the synchronized clock enable signal SYNC_CKE outputted from the synchronization section 100 through a second input terminal, to execute a NAND operation, and to output the internal clock signal INT_CLK.
FIG. 2 is a timing diagram illustrating the operation of the conventional circuit for generating an internal clock signal by buffering an external clock signal shown in FIG. 1.
Referring to FIG. 2, it is to be understood that the external clock signal EXT_CLK toggles with a period, while the clock enable signal CKE momentarily transits from an inactivated state of a logic low level to an activated state of a logic high level.
In this regard, if the time at which the clock enable signal CKE transits from the logic low level to the logic high level is close to an edge of the external clock signal EXT_CLK (i.e., either a falling edge or a rising edge), concerns arise about glitches that may occur in the synchronized clock enable signal SYNC_CKE outputted from the synchronization section 100, as shown in FIG. 2.
In the case where the internal clock generation section 120 is operated using the synchronized clock enable signal SYNC_CKE as shown, in which the glitches occur, the internal clock signal INT_CLK cannot be properly generated. In other words, where the synchronized clock enable signal SYNC_CKE has glitches, the internal clock signal INT_CLK is generated with glitches occurring therein as shown in FIG. 2.
As the frequency of the external clock signal EXT_CLK becomes high, these glitches may markedly influence the operation of an entire semiconductor device.
FIG. 3 is a timing diagram illustrating an operation of the conventional clock buffering circuit shown in FIG. 1.
FIG. 3 shows the buffering operations in a case in which the clock enable signal CKE transits from an activated state of a logic high level to an inactivated state of a logic low level.
As shown in FIG. 3, if the clock enable signal CKE transits from an activated state of a logic high level to an inactivated state of a logic low level (i.e., at a falling edge) at substantially the same time in which the external clock signal EXT_CLK transits from an inactivated state of a logic low level to an activated state of a logic high level (i.e., at a rising edge), a concern arises regarding the generation of the internal clock signal INT_SIGNAL. As identified by the circled number {circle around (1)} in the drawing, the generated internal clock signal INT_CLK cannot have a precise logic level due to a glitch which occurs in the course of generating the synchronized clock enable signal SYNC_CKE by synchronizing the clock enable signal CKE with the clock signal /EXT_CLK obtained by inverting the phase of the external clock signal EXT_CLK, and a glitch which occurs in the course of generating the internal clock signal INT_CLK by executing the NAND operation between the synchronized clock enable signal SYNC_CKE and the external clock signal EXT_CLK.
More specifically, due to the occurrence of the glitches, the time at which the synchronized clock enable signal SYNC_CKE transits from an activated state of a logic high level to an inactivated state of a logic low level (i.e., at the time of a falling edge) lags the time at which the external clock signal EXT_CLK transits from an inactivated state of a logic low level to an activated state of a logic high level (i.e., at the time of a rising edge), by an amount of time that cannot be known in advance. Due to this fact, after the internal clock signal INT_CLK transits from an inactivated state of a logic low level to an activated state of a logic high level in correspondence with the external clock signal EXT_CLK, the internal clock signal INT_CLK transits from an activated state of a logic high level to an inactivated state of a logic low level. Thus, the internal clock signal INT_CLK cannot maintain a normal toggling interval.
In this way, in the conventional clock buffering circuit, if the time at which the logic level of the external clock signal EXT_CLK transits and the time at which the clock enable signal CKE toggles are close to each other, a pulse may be generated such that the internal clock signal INT_CLK cannot be recognized as a normal clock signal, and due to this fact, an entire semiconductor device may malfunction.
FIG. 4 is a timing diagram illustrating another operation of the conventional clock buffering circuit shown in FIG. 1.
FIG. 4 shows the buffering operations in a case in which the clock enable signal CKE transits from an inactivated state of a logic low level to an activated state of a logic high level.
As shown in FIG. 4, if the clock enable signal CKE transits from an inactivated state of a logic low level to an activated state of a logic high level (i.e. at a rising edge) at substantially the same time in which the external clock signal EXT_CLK transits from an inactivated state of a logic low level to an activated state of a logic high level (i.e., at a rising edge), a concern arises regarding the generation of the internal clock signal INT SIGNAL. As identified by the circled number {circle around (1)} in the drawing, the generated internal clock signal INT_CLK cannot have a normal activation interval due to a glitch which occurs in the course of generating the synchronized clock enable signal SYNC_CKE by synchronizing the clock enable signal CKE with the clock signal /EXT_CLK obtained by inverting the phase of the external clock signal EXT_CLK, and a glitch which occurs in the course of generating the internal clock signal INT_CLK by executing the NAND operation between the synchronized clock enable signal SYNC_CKE and the external clock signal EXT_CLK.
More specifically, due to the occurrence of the glitches, the time at which the synchronized clock enable signal SYNC_CKE transits from an inactivated state of a logic low level to an activated state of a logic high level (i.e., at the time of a rising edge) lags the time at which the external clock signal EXT_CLK transits from an inactivated state of a logic low level to an activated state of a logic high level (i.e., at the time of a rising edge), by an amount of time that cannot be known in advance. Due to this fact, the time at which the internal clock signal INT_CLK transits from an inactivated state of a logic low level to an activated state of a logic high level, in correspondence with the external clock signal EXT_CLK, is shifted backward. Thus, the internal clock signal INT_CLK cannot maintain a normal toggling interval.
In this way, in the conventional clock buffering circuit, if the time at which the logic level of the external clock signal EXT_CLK transits and the time at which the clock enable signal CKE toggles are close to each other, a pulse can be generated such that the internal clock signal INT_CLK cannot be recognized as a normal clock signal, and due to this fact, an entire semiconductor device may malfunction.